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74LVC1G57
Low-power configurable multiple function gate
Rev. 01 -- 6 September 2004 Product data sheet
1. General description
The 74LVC1G57 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74LVC1G57 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer. All inputs can be connected to VCC or GND. All inputs (A, B and C) have Schmitt-trigger action. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
2. Features
s s s s Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: x JESD8-7 (1.65 V to 1.95 V) x JESD8-5 (2.3 V to 2.7 V) x JESD8B/JESD36 (2.7 V to 3.6 V). 24 mA output drive (VCC = 3.0 V) ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from -40 C to +85 C and -40 C to +125 C.
s s
s s s s s s
Philips Semiconductors
74LVC1G57
Low-power configurable multiple function gate
3. Quick reference data
Table 1: Quick reference data GND = 0 V; Tamb = 25 C; tr = tf 2.5 ns. Symbol Parameter Conditions CL = 30 pF; RL = 1 k; VCC = 1.8 V CL = 30 pF; RL = 500 ; VCC = 2.5 V CL = 50 pF; RL = 500 ; VCC = 2.7 V CL = 50 pF; RL = 500 ; VCC = 3.3 V CL = 50 pF; RL = 500 ; VCC = 5.0 V; CI CPD
[1]
Min -
Typ 6.0 3.5 4.2 3.8 3.0 2.5 22
Max -
Unit ns ns ns ns ns pF pF
tPHL, tPLH propagation delay input A, B and C to output Y
input capacitance power dissipation capacitance per buffer VCC = 3.3 V
[1] [2]
-
CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = total load switching outputs; (CL x VCC2 x fo) = sum of the outputs. The condition is VI = GND to VCC.
[2]
4. Ordering information
Table 2: Ordering information Package Temperature range 74LVC1G57GW 74LVC1G57GV 74LVC1G57GM -40 C to +125 C -40 C to +125 C -40 C to +125 C Name XSON6 Description plastic surface mounted package; 6 leads plastic surface mounted package; 6 leads plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm Version SOT363 SOT457 SOT886 Type number
5. Marking
Table 3: Marking Marking code YC V57 YC Type number 74LVC1G57GW 74LVC1G57GV 74LVC1G57GM
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Product data sheet
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Philips Semiconductors
74LVC1G57
Low-power configurable multiple function gate
6. Functional diagram
3 4 B 1 Y
A
C
6
001aab583
Fig 1. Logic symbol.
7. Pinning information
7.1 Pinning
B B GND 1 2 6 C GND
1
6
C
57
2 5 VCC
57
5
VCC Y A 3 4
001aab592
A
3
001aab591
4
Y
Transparent top view
Fig 2. Pin configuration SOT363 and SOT457.
Fig 3. Pin configuration SOT886.
7.2 Pin description
Table 4: Symbol B GND A Y VCC C Pin description Pin 1 2 3 4 5 6 Description data input B ground (0 V) data input A data output Y supply voltage data input C
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74LVC1G57
Low-power configurable multiple function gate
8. Functional description
8.1 Function table
Table 5: Input C L L L L H H H H
[1]
Function table [1] Output B L L H H L L H H A L H L H L H L H Y H L H L L L H H
H = HIGH voltage level; L = LOW voltage level.
8.2 Logic configurations
Table 6: Function selection table Figure see Figure 4 see Figure 7 see Figure 5 and 6 see Figure 5 and 6 see Figure 7 see Figure 4 see Figure 8 see Figure 9 see Figure 10 Logic function 2-input AND 2-input AND with both inputs inverted 2-input NAND with inverted input 2-input OR with inverted input 2-input NOR 2-input NOR with both inputs inverted 2-input XNOR Inverter Buffer
VCC B C Y B 1 2 B C Y 3 6 5 4 Y B C Y C B C Y B 1 2 3 6 5 4 Y C
VCC
001aab584
001aab585
Fig 4. 2-input AND gate or 2-input NOR gate with both inputs inverted.
Fig 5. 2-input NAND gate with input B inverted or 2-input OR gate with inverted C input.
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Product data sheet
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74LVC1G57
Low-power configurable multiple function gate
VCC VCC A C Y A C 1 2 A C Y A 3 6 5 4 Y C A C Y A Y 1 2 3 6 5 4 Y C
001aab587 001aab586
Fig 6. 2-input NAND gate with input C inverted or 2-input OR gate with inverted A input.
Fig 7. 2-input NOR gate or 2-input AND gate with both inputs inverted.
VCC VCC B B C Y 1 2 3 6 5 4 Y A Y A
001aab588 001aab589
C 1 2 3 6 5 4 Y
Fig 8. 2-input XNOR gate.
Fig 9. Inverter.
VCC
B B Y
1 2 3
6 5 4 Y
001aab590
Fig 10. Buffer.
9. Limiting values
Table 7: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO Parameter supply voltage input diode current input voltage output diode current output voltage output source or sink current VO > VCC or VO < 0 V active mode Power-down mode VO = 0 V to VCC
[1] [2] [1] [2]
Conditions VI < 0 V
[1]
Min -0.5 -0.5 -0.5 -0.5 -
Max +6.5 -50 +6.5 50 +6.5 +6.5 50
Unit V mA V mA V V mA
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74LVC1G57
Low-power configurable multiple function gate
Table 7: Limiting values ...continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol ICC, IGND Tstg Ptot
[1] [2]
Parameter VCC or GND current storage temperature power dissipation
Conditions
Min -65
Max 100 +150 300
Unit mA C mW
Tamb = -40 C to +125 C
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
10. Recommended operating conditions
Table 8: Symbol VCC VI VO Recommended operating conditions Parameter supply voltage input voltage output voltage active mode VCC = 0 V; Power-down mode Tamb operating ambient temperature Conditions Min 1.65 0 0 0 -40 Typ Max 5.5 5.5 VCC 5.5 +125 Unit V V V V C
11. Static characteristics
Table 9: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol VOL Parameter LOW-level output voltage Conditions VI = VCC or GND IO = 100 A; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V VOH HIGH-level output voltage VI = VCC or GND IO = -100 A; VCC = 1.65 V to 5.5 V IO = -4 mA; VCC = 1.65 V IO = -8 mA; VCC = 2.3 V IO = -12 mA; VCC = 2.7 V IO = -24 mA; VCC = 3.0 V IO = -32 mA; VCC = 4.5 V ILI input leakage current VI = 5.5 V or GND; VCC = 3.6 V VCC - 0.1 1.2 1.9 2.2 2.3 3.8 0.1 5 V V V V V V A 0.1 0.45 0.3 0.4 0.55 0.55 V V V V V V Min Typ Max Unit Tamb = -40 C to +85 C [1]
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74LVC1G57
Low-power configurable multiple function gate
Table 9: Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Ioff ICC ICC CI VOL Parameter power OFF leakage current quiescent supply current additional quiescent supply current per pin input capacitance LOW-level output voltage VI = VCC or GND IO = 100 A; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V VOH HIGH-level output voltage VI = VCC or GND IO = -100 A; VCC = 1.65 V to 5.5 V IO = -4 mA; VCC = 1.65 V IO = -8 mA; VCC = 2.3 V IO = -12 mA; VCC = 2.7 V IO = -24 mA; VCC = 3.0 V IO = -32 mA; VCC = 4.5 V ILI Ioff ICC ICC input leakage current power OFF leakage current quiescent supply current additional quiescent supply current per pin VI = 5.5 V or GND; VCC = 3.6 V VI or VO = 5.5 V; VCC = 0 V VI = VCC or GND; IO = 0 A; VCC = 5.5 V VI = VCC - 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V VCC - 0.1 0.95 1.7 1.9 2.0 3.4 100 200 200 5000 V V V V V V A A A A 0.1 0.7 0.45 0.6 0.8 0.8 V V V V V V Conditions VI or VO = 5.5 V; VCC = 0 V VI = VCC or GND; IO = 0 A; VCC = 5.5 V VI = VCC - 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V Min Typ 0.1 0.1 5 2.5 Max 10 10 500 Unit A A A pF
Tamb = -40 C to +125 C
[1]
Typical values are measured at maximum VCC and Tamb = 25 C.
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Low-power configurable multiple function gate
12. Dynamic characteristics
Table 10: Dynamic characteristics GND = 0 V. Symbol tPHL, tPLH Parameter C [1] see Figure 11 and 12 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CPD power dissipation capacitance per buffer propagation delay A, B, C to Y VCC = 3.3 V
[2] [3]
Conditions
Min
Typ
Max
Unit
Tamb = -40 C to +85
propagation delay A, B, C to Y
1.0 0.5 0.5 0.5 0.5 -
6.0 3.5 4.2 3.8 3.0 22
14.4 8.3 8.5 6.3 5.1 -
ns ns ns ns ns pF
Tamb = -40 C to +125 C tPHL, tPLH see Figure 11 and 12 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V
[1] [2] Typical values are measured at nominal VCC and Tamb = 25 C. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = total load switching outputs; (CL x VCC2 x fo) = sum of the outputs. The condition is VI = GND to VCC.
1.0 0.5 0.5 0.5 0.5
-
18 10.4 10.6 7.9 6.4
ns ns ns ns ns
[3]
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74LVC1G57
Low-power configurable multiple function gate
13. Waveforms
VI A, B, C input GND t PHL VOH Y output VOL t PLH VOH Y output VOL VM t PHL VM t PLH VM
001aab593
Measurement points are given in Table 11. VOL and VOH are typical output voltage drop that occur with the output load.
Fig 11. Input A, B and C to output Y propagation delay times. Table 11: VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V Measurement points Input VM 0.5 x VCC 0.5 x VCC 1.5 V 1.5 V 0.5 x VCC VI VCC VCC 2.7 V 2.7 V VCC Output VM 0.5 x VCC 0.5 x VCC 1.5 V 1.5 V 0.5 x VCC
Supply voltage
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74LVC1G57
Low-power configurable multiple function gate
VEXT VCC PULSE GENERATOR VI D.U.T. RT CL RL VO RL
mna616
Measurement points are given in Table 12. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. VEXT = Test voltage for switching times.
Fig 12. Load circuitry for switching times. Table 12: VCC 1.65 V to 1.95 V 2.3 to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V Measurement points Input VI VCC VCC 2.7 V 2.7 V VCC tr = t f 2.0 ns 2.0 ns 2.5 ns 2.5 ns 2.5 ns Load CL 30 pF 30 pF 50 pF 50 pF 50 pF RL 1 k 500 500 500 500 VEXT tPLH, tPHL tPZH, tPHZ tPZL, tPLZ open open open open open GND GND GND GND GND 2 x VCC 2 x VCC 6V 6V 2 x VCC
Supply voltage
14. Transfer characteristics
Table 13: Transfer characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol VT+ Parameter C [1] see Figure 13, 14, 15 and 16 VCC = 1.8 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V VCC = 5.5 V VT- negative-going threshold voltage see Figure 13, 14, 15 and 16 VCC = 1.8 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V VCC = 5.5 V 0.30 0.58 0.80 1.21 1.45 0.53 0.77 1.04 1.55 1.86 0.72 1.00 1.30 1.90 2.29 V V V V V 0.70 1.11 1.50 2.16 2.61 1.02 1.42 1.79 2.52 2.99 1.20 1.60 2.00 2.74 3.33 V V V V V positive-going threshold voltage Conditions Min Typ Max Unit Tamb = -40 C to +85
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74LVC1G57
Low-power configurable multiple function gate
Table 13: Transfer characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol VH Parameter hysteresis voltage (VT+ - VT-) Conditions see Figure 13, 14, 15 and 16 VCC = 1.8 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V VCC = 5.5 V Tamb = -40 C to +125 C VT+ positive-going threshold voltage see Figure 13, 14, 15 and 16 VCC = 1.8 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V VCC = 5.5 V VT- negative-going threshold voltage see Figure 13, 14, 15 and 16 VCC = 1.8 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V VCC = 5.5 V VH hysteresis voltage (VT+ - VT-) see Figure 13, 14, 15 and 16 VCC = 1.8 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V VCC = 5.5 V
[1] Typical values are measured at Tamb = 25 C.
Min 0.30 0.40 0.50 0.71 0.71
Typ 0.48 0.64 0.75 0.97 1.13
Max 0.62 0.80 1.00 1.20 1.40
Unit V V V V V
0.67 1.08 1.47 2.13 2.58 0.30 0.58 0.80 1.21 1.45 0.23 0.34 0.44 0.65 0.65
-
1.20 1.60 2.00 2.74 3.33 0.75 1.03 1.33 1.93 2.32 0.62 0.80 1.00 1.20 1.40
V V V V V V V V V V V V V V V
15. Waveforms transfer characteristics
VO
VI
VT+ VT- VH
VO VH VT- VT+ VI
mna207 mna208
VT+ and VT- limits are at 70 % and 20 %.
Fig 13. Transfer characteristic.
9397 750 13722
Fig 14. Definition of VT+, VT- and VH.
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Product data sheet
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74LVC1G57
Low-power configurable multiple function gate
VO
VI
VT+ VH VT-
VO VI VT+
mnb154
VH VT-
mnb155
VT+ and VT- limits are at 70 % and 20 %.
Fig 15. Transfer characteristic.
Fig 16. Definition of VT+, VT- and VH.
16 I CC (mA) 12
001aab594
8
4
0 0 1 2 VI (V) 3
Fig 17. Typical 74LVC1G57 transfer characteristic; VCC = 3.0 V.
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74LVC1G57
Low-power configurable multiple function gate
16. Package outline
Plastic surface mounted package; 6 leads SOT363
D
B
E
A
X
y
HE
vMA
6
5
4
Q
pin 1 index
A
A1
1
e1 e
2
bp
3
wM B detail X Lp
c
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.30 0.20 c 0.25 0.10 D 2.2 1.8 E 1.35 1.15 e 1.3 e1 0.65 HE 2.2 2.0 Lp 0.45 0.15 Q 0.25 0.15 v 0.2 w 0.2 y 0.1
OUTLINE VERSION SOT363
REFERENCES IEC JEDEC EIAJ SC-88
EUROPEAN PROJECTION
ISSUE DATE 97-02-28
Fig 18. Package outline SOT363.
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Product data sheet
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74LVC1G57
Low-power configurable multiple function gate
Plastic surface mounted package; 6 leads
SOT457
D
B
E
A
X
y
HE
vMA
6
5
4
Q
pin 1 index
A A1 c
1
2
3
Lp
e
bp
wM B detail X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 0.1 0.013 bp 0.40 0.25 c 0.26 0.10 D 3.1 2.7 E 1.7 1.3 e 0.95 HE 3.0 2.5 Lp 0.6 0.2 Q 0.33 0.23 v 0.2 w 0.2 y 0.1
OUTLINE VERSION SOT457
REFERENCES IEC JEDEC EIAJ SC-74
EUROPEAN PROJECTION
ISSUE DATE 97-02-28 01-05-04
Fig 19. Package outline SOT457.
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74LVC1G57
Low-power configurable multiple function gate
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b 1 2 3 4x L1 L
(2)
e
6 e1
5 e1
4
6x
(2)
A
A1 D
E
terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 1.5 1.4 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm
Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC MO-252 JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22
Fig 20. Package outline SOT886 (XSON6).
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Low-power configurable multiple function gate
17. Revision history
Table 14: Revision history Release date 20040906 Data sheet status Product data sheet Change notice Doc. number 9397 750 13722 Supersedes Document ID 74LVC1G57_1
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Low-power configurable multiple function gate
18. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
19. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
20. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
21. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
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Low-power configurable multiple function gate
22. Contents
1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 9 10 11 12 13 14 15 16 17 18 19 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Logic configurations . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Transfer characteristics. . . . . . . . . . . . . . . . . . 10 Waveforms transfer characteristics . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information . . . . . . . . . . . . . . . . . . . . 17
(c) Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 6 September 2004 Document number: 9397 750 13722
Published in The Netherlands

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